Instruction

Abstract

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• Also known as Machine Codes
• Bit String
• Passed to CPU to get translated to carry out Operation
• Doesn’t specify which CPU Datapath does what, just specify what outputs are expected with a given input
• The instruction lifecycle can be broken down into Pipeline Stages
• 2 forms - Fixed-length & Variable-length

2 Parts

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Opcode

• Config for Control Signal
• MIPS, 6-bits, 2^6 → 64 combinations

Parameter

• Register Address
• Memory Address
• Immediate Value

Terminologies

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Branch

• An Instruction that causes Process (进程) to jump to a different location in the codes

Fixed-length

• Easy Fetch & Decode
• Simplified Pipeline & Instruction-Level Parallelism

Variable-length

• More Flexible BUT Requires more steps for Fetch & Decode

Single Instruction Multiple Data

• This allows one Instruction to operate on multiple data at once and have multiple outputs essentially
• This can reduce the number of instructions in a program significantly, and have more data processed without the involvement of the inefficient Main Memory

Expanding Opcode Scheme

• The Opcode in an Instruction can be extended to accommodate additional instructions in the future without changing the basic format of the instruction set

References

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• Reinventing the Processor